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pt6552 ? duty lcd driver with on-chip key input function tel: 886-66296288 ? fax: 886-29174598 ? http://www.princeton.com.tw ? 2f, 233-1, baociao road, sindian, taipei 23145, taiwan description the pt6552 is ? duty dynamic lcd display driver. in addition to being able to directly drive lcd panels with up to 90 segments, it can also control up to 4 general purpose output ports. this product also includes a key scan circuit that allows it to accept input from keypads with up to 30 keys. this allows the end product front panel wiring to be simplified. applications ? cellular phone ? data bank, organizer ? electronic dictionary/translator ? p.d.a. ? p.o.s. ? information appliance ? caller id ? pager ? electronic equipment with lcd display features ? up to 4 general purpose output ports ? up to 90 segments outputs ? up to 30 key inputs (key scan is only performed when a key is pressed) ? ? duty - ? bias (up to 90 segments) ? serial data control sleep mode and the all segments off function ? serial data controlled segment output port/general-purpose output port usage ? serial data i/o supports ccb format communication with the system controller ? high generality since display data is displayed directly without decoder intervention ? reset pin that can establish the initial state ? available in 64 pin qfp and 64 pin lqfp package block diagram
pt6552 v1.3 2 july 2010 application circuit note: * since do is an open-drain output, a pull-up resistor is required. select a value (between 1k and 10k ? ) that is appropriate for the capacitance of the external wiring so that the waveforms are not distorted.
pt6552 v1.3 3 july 2010 order information valid part number package type top code pt6552 64 pin, qfp pt6552 PT6552LQ 64 pin, lqfp PT6552LQ pin configuration
pt6552 v1.3 4 july 2010 pin configurations pin name i/o function active handing when unused pin no. sg1/p1 to sg4/p4 sg5 to sg43 o segment outputs: used to output the display data that is transmitted over the serial data input. pins sg1/p1 to sg4/p2 can be used as general-purpose outputs according to control data specification. - open 1 to 4 5 to 43 com1 com2 o common driver outputs. the frame frequency fo is (fosc/512)hz - open 44 45 ks1/sg44, ks2/sg45, ks3 to ks6 o key scan outputs. when a key matrix is formed, normally a diode will be attached to the key scan timing line to prevent shorts. however, since the output transistor impedance is an unbalanced cmos output, it will not be damaged if shorted. pins ks1/sg44 and ks2/sg45 can be used as segment outputs according to control data specification. - open 46 47 48 to 51 ki1 to ki5 i key scan inputs: pin with a built-in pull-down resistor. h gnd 52 to 56 osc i/o oscillator connection: oscillator circuit can be formed by connecting the pin to a resistor and a capacitor - v dd 57 v ss - power supply ground connected. must be connected to gnd. - - 58 /res i reset input that re-initializes the lsi internal states. during a reset, the display segments are turned off forcibly regardless of the internal display data. all internal key data is reset to low and the key scan operation is disabled. however, serial data can input during a reset. l gnd 59 v dd - power supply connection. a supply voltage of between 4.5 and 6.0v must be provided. - - 60 do o serial data interface: connected to the controller. since do is an open-drain output, it required a pull-up resistor. ce: chip enable clk: synchronization clock di: transfer data do: output data - open 61 ce i h gnd 62 clk i 63 di i - 64
pt6552 v1.3 5 july 2010 function description serial data input when stopped with clk at the low level when stopped with clk at the high level ccb address: 42h d1 to d90: display data s0, s1: sleep control data k0, k1: key scan output/segment output selection data p0, p1: segment output port/general-purpose output port selection data sc: segment on/off control data
pt6552 v1.3 6 july 2010 control serial data function 1. s0, s1: sleep control data this control data switches the lsi between normal mode and sl eep mode. it also sets the key scan output standby states for pinsks1 to ks6. control data mode oscillator segment outputs common outputs key scan standby mode output pin states s0 s1 ks1 ks2 ks3 ks4 ks5 ks6 0 0 normal oscillator operation h h h h h h 0 1 sleep stopped l l l l l l h 1 0 sleep stopped l l l l l h h 1 1 sleep stopped l h h h h h h 2. k0, k1: key scan output/seg ment output selection data this control data switches the ks1/sg44 and ks2/sg45 out put pins between the key scan output and segment output function. control data output pin states maximum number of key inputs k0 k1 ks1/sg44 ks2/sg45 0 0 ks1 ks2 30 0 1 sg44 ks2 25 1 x sg44 sg45 20 x: don?t care 3. p0, p1: segment output port /general-purpose output port selection data this control data switches the sg1/p1 to sg4/p4 output pins between the segment output port and the general-purpose output port function. control data output pin states p0 p1 sg1/p1 sg2/p2 sg3/p3 sg4/p4 0 0 sg1 sg2 sg3 sg4 0 1 p1 p2 sg3 sg4 1 0 p1 p2 p3 sg4 1 1 p1 p2 p3 p4 the table below lists the correspondence between the displa y data and the output pins when the general-purpose output port function is selected. output pin corresponding display data sg1/p1 d1 sg2/p2 d3 sg3/p3 d5 sg4/p4 d7 for example, if the output pin sg4/p4 is set for use as a general-purpose output port, the output pin sg4/p4 will output a high level when the display data d7 is 1. 4. sc: segment on/off control data this control data controls the segment on/off states. sc display states 0 on 1 off
pt6552 v1.3 7 july 2010 display data l serial data function output pin com1 com2 sg1/p1 d1 d2 sg2/p2 d3 d4 sg3/p3 d5 d6 sg4/p4 d7 d8 sg5 d9 d10 sg6 d11 d12 sg7 d13 d14 sg8 d15 d16 sg9 d17 d18 sg10 d19 d20 sg11 d21 d22 sg12 d23 d24 sg13 d25 d26 sg14 d27 d28 sg15 d29 d30 sg16 d31 d32 sg17 d33 d34 sg18 d35 d36 sg19 d37 d38 sg20 d39 d40 sg21 d41 d42 sg22 d43 d44 sg23 d45 d46 sg24 d47 d48 sg25 d49 d50 sg26 d51 d52 sg27 d53 d54 sg28 d55 d56 sg29 d57 d58 sg30 d59 d60 sg31 d61 d62 sg32 d63 d64 sg33 d65 d66 sg34 d67 d68 sg35 d69 d70 sg36 d71 d72 sg37 d73 d74 sg38 d75 d76 sg39 d77 d78 sg40 d79 d80 sg41 d81 d82 sg42 d83 d84 sg43 d85 d86 ks1/sg44 d87 d88 ks2/sg45 d89 d90 for example, the output states of output pin sg11 are listed in the table below. display data output pin state d21 d22 sg11 0 0 segment off for both com1 and com2 0 1 segment on for com2 1 0 segment on for com1 1 1 segment on for both com1 and com2
pt6552 v1.3 8 july 2010 serial data output when stopped with clk at the low level when stopped with clk at the high level ccb address: 43h kd1 to kd30: key data sa: sleep acknowledge data note: if key data is read when do is high, the key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid.
pt6552 v1.3 9 july 2010 output data kd1 to kd30: key data when a key matrix with up to 30 keys is formed using the ks1 to ks6 output pins and the ki1 to ki5 input pins, the key data corresponding to gi ven key will be 1 if that key is pressed. the table below lists that corres pondence. item ki1 ki2 ki3 ki4 ki5 ks1/sg44 kd1 kd 2 kd3 kd4 kd5 ks2/sg45 kd6 kd7 kd8 kd9 kd10 ks3 kd11 kd12 kd 13 kd14 kd15 ks4 kd16 kd17 kd 18 kd19 kd20 ks5 kd21 kd22 kd 23 kd24 kd25 ks6 kd26 kd27 kd 26 kd29 kd30 when the output pins ks1/sg44 and ks2/sg45 are selected fo r segment output by the cont rol data k0 and k1, the key data items kd1 to kd10 will be 0. sa: sleep acknowledge data this output data is set according to the state when the ke y was pressed. if the lsi was in sleep mode, sa will be 1, and if the lsi was in normal mode, sa will be 0. sleep mode when s0 or s1 in the control data is set to 1, the oscillator at the osc pin will stop (it will restart if a key is pressed) an d the segment and common outputs will all go to the low level. this reduces the lsi power dissipation. however, the sg1/p1 to sg4/p4 output pins can be used as general-purpose output ports even in sleep mode if selected for such use by the p0 and p1 control data bits key scan operating key scan timing the key scan period is 375t[s]. the key scan is performed tw ice to reliably determine the key on/off states, and the lsi detects key data agreement. when the key data agrees, the lsi determines that a key has been pressed, and outputs a key read request (by setting do low) 800t[s] after the key scan started. if a key is pressed again without the key data agreeing, a key scan is performed 1=once more. thus key on/ off operations shorter than 800t[s] cannot be detected. note: *1: the high or low states of these signals in sleep m ode are determined by the s0 and s1 control data bits.
pt6552 v1.3 10 july 2010 key scan during normal mode the pins ks1 to ks6 are set high. a key scan starts if any key is pressed, and the scan continues until all keys have been released. multiple key pressed can be recognized be determi ning if multiple key data bits have been set. when a key has been pressed for 800t[s] (when t=1/fosc) or longer, a key data read request (do is set to low) is output to the controller. the controller acknowledges this request and reads the ke y data; however, do will go high when ce is high during a serial data transfer. after the controller has finished reading the key data, the lsi clears the key data read request (by setting do high) and performs another key scan. note that since do is an open drain output, a pull-up resistor of between 1k and 10k ? is required. key scan during sleep mode the pins ks1 to ks6 are set high or low according to the s0 and s1 control data bits. (see the description of the control data function for details)if a key for a line corresponding to one of the pins ks1 to ks6 which is high is pressed, the oscillator at the osc pin starts and a key scan is performed. the key scan conti nues until all keys have been released. multiple key presses can be recognized by determining if multiple key data bits have been set. when a key has been pressed for 800t[s] (where t=1/fosc) or longer, a key data read request (d0 is set to low) is output to the controller. the controller acknowledges this request and reads the key data; however, do will go high when ce is high during a serial data transfer. after the controller has finished reading the ke y data, the lsi clears the key data read request (by setting do high) and performs another key scan. note that since do is an open drain output, a pull-up resistor of between 1k and 10k ? is required. key scan example in sleep mode. example: here s0 = 0 and s1 = 1 (this is a sleep in which only ks6 is high) note: *1=these diodes are required to reliably recognize events in which three or more of the keys on the ks6 line are pressed at the same time.
pt6552 v1.3 11 july 2010 multiple key presses without the insertion of additional diode s, the pt6552 supports key scan for double key presses in general, triple key presses of keys on the lines for input pins ki1 to ki5, and mult iple key pressed of keys on the lines for the output pins ks1 to ks6. however, if multiple key presses in excess of thes e limits occur, the pt6552 may recognize keys that were not pressed as having been pressed. therefore, se ries diodes must be connected to each key. ? duty ? ? bias lcd drive scheme
pt6552 v1.3 12 july 2010 nternal block states during the reset period (when /res is low) clock generator reset is applied and the basic clock stops. however, the stat e of the osc pin (the normal or sleep state) is determined after the control data s0 and s1 has been sent. common driver, segment driver & latch reset is applied and the display is turned off. ho wever, display data can be input to the latch. key scan reset is applied and at the same time as the internal stat es are set to their initial states, the key scan operation is disabled. key buffer reset is applied and all the key data is set to the low level. ccb interface, control register, shift register to allow serial data transfers, reset is not applied to these circuits.
pt6552 v1.3 13 july 2010 output pin states during the reset period (when /res is low) output pin state during reset sg1/p1 to sg4/p4 l *1 sg5 to sg43 l com1, com2 l ks1/sg44, ks2/sg45 l *1 ks3 to ks5 x *2 ks6 h do h *3 x: don?t care notes: *1: these output pins are forcibly set to the segment output mode and held low. *2: immediately following power on, these output pins ar e undefined until the control data s0 and s1 has been sent. *3: since this output pin is an open-drain out put, a pull-up resistor of between 1k and 10k ? is required. this pin is held high during the reset period even if key data is read. note on controller display data transfer the pt6552 transfers the display data (d1 to d90) in two operat ions. to assure visual display quality, all the display data should be sent within a 30ms or shorter period.
pt6552 v1.3 14 july 2010 note on controller ke y data read techniques when determining key on/off and reading key data, the controller must confirm the state of d0 output when ce is low for each period t7. when do is low, the controller recognizes t hat a key has been pressed and reads the key data. during this operation t7 must obey the following condition: t7 > t5 + t6 + t4 if key data is read when do is high, the key data (kd1 to kd30) and the sleep acknowledge data (sa) will be invalid. 1. controller key data re ading under timer control flowchart timing chart t=1/fosc t3: key scan execution time (800t [s]) when the key scan data for two key scans agrees. t4: key scan execution time (1600t [s]) when the key sca n data for two key scans does not agree and a key scan is executed again. t5: key address (43h) transfer time. t6: key data read time.
pt6552 v1.3 15 july 2010 2. controller key data readi ng under interrupt control when determining key on/of and reading key data, the controller must confirm the state of do output when ce is low. when do is low, the controller recognizes that a key has been pressed and reads the key data. after the time t8, the next key on/off determination and reading key data must be confirmed by the state of do output when ce is low. during this operation t8 must obey the following condition: t8 > t4. if key data is read when do is high, the key data (kd1 to kd30) and the sleep acknowledge data (sa) be invalid. flowchart timing chart t=1/fosc t3: key scan execution time (800t [s]) when the key scan data for two key scans agrees. t4: key scan execution time (1600t [s]) when the key sca n data for two key scans does not agree and a key scan is executed again. t5: key address (43h) transfer time. t6: key data read time.
pt6552 v1.3 16 july 2010 /res and the display controller since the lsi internal data (d1 to d90 and the control data) is undefined when power is first applied, the output pins sg1/p1 to sg4/p4, sg5 to sg43, com1, com2, ks1/sg 44 and ks2/sg45 should be held low by setting the /res pin low at the same time as power is applied. then, meaningles s displays at power on can be prevented by transferring data from the controller and setting /res high when that transfer has completes. t1: determined by the value of c and r t2: 10 s min figure 1
pt6552 v1.3 17 july 2010 absolute maximum ratings (vss=0v, ta=25 ) parameter symbol condition rating unit maximum supply voltage v dd max v dd -0.3 ~ +7.0 v input voltage v in osc, ce, clk, di, /res, ki1 to ki5 -0.3 to v dd +0.3 v output voltage v out osc, do, sg1 to sg45, com1, com2, ks1 to ks6, p1 to p4 -0.3 to v dd +0.3 v output current i out1 sg1 to sg45 100 a i out2 com1, com2, ks1 to ks6 1 ma i out3 p1 to p4 5 ma allowable power dissipation pd max ta=85 200 mw operating temperature topr -40 to +85 storage temperature tstg -65 to +150 allowable operating ranges (ta=-40 to +85 , vss=0v) parameter symbol condition min. typ. max. unit supply voltage v dd v dd 4.5 6.0 v input high-level voltage v ih1 ce, clk, di, /res 0.8v dd v dd v v ih2 ki1 to ki5 0.6v dd v dd v input low-level voltage v il ce, clk, di, /res, ki1 to ki5 0 0.2v dd v recommended external resistance r osc osc 62 k ? recommended external capacitance c osc osc 680 pf guaranteed oscillator range fosc osc 25 50 100 khz data setup time t ds clk, di: figure 2 160 ns data hold time t dh clk, di: figure 2 160 ns ce wait time tcp ce, clk: figure 2 160 ns ce setup time tcs ce, clk: figure 2 160 ns ce hold time tch ce, clk: figure 2 160 ns high-level clock pulse width t ? h clk: figure 2 160 ns low-level clock pulse width t ? l clk: figure 2 160 ns rise time t r ce, clk, di: figure 2 160 ns fall time t f ce, clk, di: figure 2 160 ns do output delay time t dc do, r pu =47k ? , c l =10pf*: figure 2 1.5 s do rise time t dr do, r pu =47k ? , c l =10pf*: figure 2 1.5 s /res switching time t 2 figure 1 10 s
pt6552 v1.3 18 july 2010 electrical characteristics in the allowable operating ranges parameter symbol condition min typ max unit hysteresis v h ce, clk, ci, /res, ki1 to ki5 0.1v dd v input high-level current i ih ce, clk, di, /res: v i =v dd 5.0 a input low-level current i il ce, clk, di, /res: v i =0v -5.0 a input floating voltage v if ki1 to ki5 0.05v dd v pull-down resistance r pd ki1 to ki5:v dd =5.0v 50 100 250 k ? output off leakage current i offh do:v o =6.0v 6.0 a output high-level voltage v oh1 ks1 to ks6:i o =-1ma v dd -1.0 v v oh2 p1 to p4:i o =-1ma v dd -1.0 v v oh3 sg1 to sg45: i o =-10 a v dd -1.0 v v oh4 com1, com2: i o =-100 100 a 2.4 3.0 3.6 v v mid2 com1, com2: v dd =4.5v, i o = 100 a 1.65 2.25 2.85 v current drain i dd1 sleep mode, ta=25 5 a i dd2 v dd =6.0v, output open, ta=25 , fosc=50 khz 1.4 2.5 ma
pt6552 v1.3 19 july 2010 when stopped with cl at the low level when stopped with cl at the high level figure 2
pt6552 v1.3 20 july 2010 package information 64 pins, qfp symbol min. nom. max. a - - 3.15 a1 0.00 - 0.25 a2 1.90 - 2.90 b 0.29 0.35 0.41 c 0.11 - 0.23 d 17.20 bsc d1 14.00 bsc e 17.20 bsc e1 14.00 bsc e 0.80 bsc l 0.65 - 1.05 l1 1.60 ref 0 - 8 notes: 1. refer to jedec mc-022be 2. unit: mm
pt6552 v1.3 21 july 2010 64 pins, lqfp symbol min. nom. max. a - - 1.60 a1 0.05 - 0.15 a2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 - 0.20 d 12.00 bsc d1 10.00 bsc e 12.00 bsc e1 10.00 bsc e 0.50 bsc l 0.45 0.60 0.75 l1 1.00 ref 0 3.5 7 notes: 1. all dimensions are in millimeter. 2. refer to jedec ms-026bcd
pt6552 v1.3 22 july 2010 important notice princeton technology corporation (ptc) reserves the ri ght to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product wi thout notice at any time. ptc cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ptc product. no circuit patent licenses are implied. princeton technology corp. 2f, 233-1, baociao road, sindian, taipei 23145, taiwan tel: 886-2-66296288 fax: 886-2-29174598 http://www.princeton.com.tw

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